1. Field of the Invention
The present invention relates to the offset calibration and auto-zeroing, and more particularly to offset calibration and auto-zeroing in flash analog to digital converters utilized in data transmission systems such as, for example, data communications channels and optical disc data storage systems using data channel circuits.
2. Description of Related Art
In many data detection circuits an electrical signal-is received from a data storage media, such as a CD-ROM, DVD, or other optical disk, magnetic hard disk, magnetic tape etc. In the case of optical disks, the electrical signal is generated from light that is reflected off an optical disk and converted to electrical pulses. The electrical pulses may then be transmitted to a data detection circuit for further signal processing to recover the data in a useable form. Data detection circuits may also be combined with circuitry for write operations. For example, circuitry for both read and write operations may be combined read/write channel circuits utilized with magnetic hard disks. In contrast, some optical disks are utilized in read only systems and thus the data detection circuit need not be combined with write circuitry. In general, both read only and read/write data detection circuits may also include servo circuitry.
Decoding the pulses into a digital sequence can be performed by a simple peak detector in an analog read channel or, as in more recent designs, by using a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interferences (ISI) and, therefore, can recover pulses recorded at high densities. As a result, discrete time sequence detectors increase the capacity and reliability of the storage system.
There are several well known discrete time sequence detection methods for use in a sampled amplitude read/write channel circuit including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, partial response maximum likelihood (PRML) sequence detection, decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF). When discrete methods are utilized for sampled amplitude read channel systems, an analog to digital converter (ADC) is typically utilized to convert the high frequency data which is contained on disk.
One type of ADC which may be utilized to convert high frequency disk data is a flash ADC. Such an ADC may contain multiple comparators for conversion of the analog data to digital data. A flash ADC may be designed in a number of manners. For example, an exemplary six bit flash analog to digital converter 100 is shown in FIG. 1. The ADC 100 includes an analog input 102 and a reference voltage input 104. The reference voltage is divided into 2n separate voltages through a series of resistors 106 which form a resistor voltage divider. Output taps are provided from the resistor voltage divider to provide reference voltage inputs 108 to a series of 2nxe2x88x921 comparators 110. The output of an ADC having 2n reference voltages and 2nxe2x88x921 comparators will have n bits. In one common ADC, illustrated in FIG. 1 in which n equals 6, sixty-four separate voltages are provided through sixty-four resistors 106 (each voltage varying by {fraction (1/64)} of the reference voltage 104 from the adjacent resistor) to inputs to the sixty-three comparators 110. The analog input 102 which is to be converted to a digital value is provided through another input to each of the comparators 110. Each comparator 110 receives control signals as shown by a control bus line 112. The control signal may include a clock signal operating at the system read operation clock speed (for example typically between 50 MHz and 1 GHz) and other control signals. The output of each comparator 110 is a binary state (high or low) which indicates whether the analog input 102 is greater than or less than the particular reference voltage 108 that is input to the comparator 110. The outputs 112 of the comparators 110, forming a thermometer code, are provided to digital encoding logic 114. By observing where the outputs of the comparators 110 change from one digital state to the other, the encoder 114 determines between which two reference voltages the analog input lies and provides a 6-bit digital representation of a voltage that represents, for example, the lower or higher reference voltage or a midpoint voltage. The 6-bit representation may then be provided, through clocked D flip-flops 116, on an output line as the ADC output 118. The digital encoding logic 114 may also include bubble suppression logic. It will be appreciated that n can be an integer other than 6. However, 6-bit ADCs are commonly employed in optical storage devices, such as that which may incorporate the ADC 100 of FIG. 1, and n=6 will be used to illustrate the ADCs herein.
In order to accurately convert the high frequency analog data, it is desirable that the comparators exhibit very little electrical variation from ideal operation even in the presence of xe2x80x9coffsetsxe2x80x9d. Many sources exist for offsets including mismatch between two devices (for example transistors, resistors, capacitors, etc.) which, though intended to be identical, vary to one degree or another due to limitations of fabrication processes.
One approach to compensate for such offsets is to utilize a DC auto-zero operation. FIG. 2 shows an example of a typical comparator configuration in a flash ADC 200. The ADC circuit 200 contains a gm stage 202 capacitively coupled to an analog input and reference levels through input switches. The ADC circuit 200 is shown differentially with two inputs and two reference voltages plus two outputs. During normal operation, the gm stage 202, the switches SW1 and SW2, and the two input capacitors C1 and C2 act as an integrator, integrating the input signal minus the reference for a fixed amount of time. The output of the integrator is transmitted to a latch stage 204 to be converted to a digital signal when a latch clock is applied. The digital signal will be one if the positive output is higher than the negative output and a zero if the negative output is higher than the positive output. Also included is a calibration circuit 208 to remove offsets and achieve higher performance with noise, clock feedthrough, offsets, and other circuit non-idealities. Auto-zero puts an initial voltage across the input capacitors C1 and C2 at regular intervals to set the appropriate reference across the input and to remove offsets in the gm stage 202. Auto-zero should repeated in order to reacquire the reference once the capacitance has leaked enough of its previous charge.
The ADC usually operates in a xe2x80x9cnormal modexe2x80x9d. Periodically (about every 475 xcexcs), it enters an auto-zero (xe2x80x9cAZxe2x80x9d) mode lasting about 50 ns. It also enters a calibration mode lasting about 1 clock periods following each AZ operation. FIGS. 3A-3C show exemplary timing signals for all three modes of operation. In FIG. 3A, representing the normal operation, signals SIG and REF, being complements of each other, are high and low, respectively; the input is sent to the comparator. AZ and CAL are both low and the signal INT and LATCH are clocked. In this configuration, the input minus the reference is integrated while INT is high; then LATCH goes high to latch the output to a digital state. FIG. 3B illustrates the timing of an AZ sequence. INT and LATCH have the same timing as shown in FIG. 3A; however, REF is brought high for several system clock cycles while SIG simultaneously low. These signals cause the input to switch to the reference signal which is tied to the resistor ladder reference. After REF is brought high, AZ is pulled high and held high for about 50 ns, then AZ goes low before the REF signal goes low to store the reference level on the input capacitor which is later used when comparing the input to the reference voltage. CAL is held low, during this mode. Finally, FIG. 3C illustrates the timing of a calibration sequence. In this mode, the timing for INT and LATCH remains the same as in FIGS. 3A and 3B. REF is held high for several system clock periods during which SIG is low. Simultaneously, AZ is held low while CAL is pulled high. The reference signal REF remains applied to the input. However, when CAL is held high, the output is examined to determine whether a positive or negative offset is required. When this CAL loop settles, there should be close to an equal number of ones and zeros from the comparator.
Understandably, it is desirable to auto-zero and calibrate the comparators of a flash ADC in such a manner so as not to impact the information that the ADC is converting. In magnetic data storage systems, such as magnetic hard disks, auto-zero and calibration operations may occur when the data channel is not in use. For example, magnetic media is generally written in concentric circles divided into sectors on a disk. Servo information is time multiplexed with user data allowing time periods to take the user data channel or the servo channel off line to perform an auto-zero or calibration operation. In data communications channels and optical storage systems (such as CD and DVD systems, for example), however, the data is generally stored in a continuous spiral on an optical disc without a sector break, both user data and servo data frequency being mutliplexed within the continuous data stream. Thus, in optical systems the data channel may be in continuous use for long periods of time without a break. In such cases, the ADC generally can not be disabled for auto-zero and calibration operations without disrupting the data stream. In order to provide for periodic calibrations of the ADC comparators, extra (or proxy or replacement) comparators may be provided via a multiplexing scheme such that if n comparators are to be utilized for the data conversion, the ADC will include at least n comparators. Thus, when one comparator is being calibrated, another comparator may be multiplexed into the ADC conversion path so that n comparators are still utilized. However, such multiplexing schemes undesirably require additional circuit complexity and disrupt the comparator array and resistor string.
In another proposed method (U.S. Pat. No. 6,084,538), individual comparators are calibrated at random or psuedo-random times while the ADC continues to perform conversions without the addition of extra xe2x80x9cproxyxe2x80x9d comparators. At periodic intervals a psuedo-random one of the comparators is disconnected or decoupled from the standard ADC circuitry for calibration. In order to prevent a significant degradation in the conversion quality, digital logic downstream of the comparators provides the necessary adjustments to accommodate the removal of one of the comparators from the data conversion path. This continuous data conversion is provided without interruption for calibration purposes.
A system and method are disclosed for calibrating and auto-zeroing comparators of an analog to digital converter. The 2nxe2x88x921 comparators of an n-bit flash ADC are divided into two banks of 2nxe2x88x921 and 2nxe2x88x921xe2x88x921 comparators, respectively, the comparators of the first bank being interleaved. with the comparators of the second bank. Control lines separately remove the first and second banks from the data conversion path for periodic calibration and auto-zeroing of the converters of the bank which has been removed. In a first embodiment, when both banks are in the data conversion path (that is, no converters are being calibrated or auto-zeroed), the outputs from both banks, each in the form of 2nxe2x88x921 or 2nxe2x88x921xe2x88x921 bit thermometer code, are processed by an encoder into the n-bit ADC output. When either bank is removed from the data conversion path to be calibrated or auto-zeroed, the encoder converts the 2nxe2x88x921xe2x88x921 or 2nxe2x88x9211 bit thermometer code from the other bank into the n-bit ADC output.
In a second embodiment, the 2nxe2x88x921 bit thermometer code output from the first bank is coupled to a first encoder and the 2nxe2x88x921xe2x88x921 bit thermometer code output from the second bank is coupled to a second encoder. The output of each encoder, nxe2x88x921 bit representations of the respective inputs, are coupled to combinatory logic. When both banks are in the data conversion path, the two nxe2x88x921 bit words output from the two encoders are combined by the logic into the n-bit ADC output. When either bank is removed from the data conversion path, the combinatory logic converts the nxe2x88x921 bit word from the other bank into the n-bit ADC output. The result, therefore, is comparable to the outputs from two 5-bit ADCs with a 0.5 bit offset.